DESCRIPTION This is a PCMCIA driver for the GEMPLUS GPR400 smartcard reader. This driver can be used along with the MUSCLE software (http://www.linuxnet.com) to provide smartcard functionality to a Linux system. INSTALLATION Unpack the files in this distribution (guess you've already done that). Build the module $ make Become root and install the module and supporting files $ su # make install Make device files if necessary. # mknod /dev/gpr400 c 123 0 LICENSE Files are released under the GNU General Public License (GPL) version 2. See the COPYING.gpr400_cs file for license details. Please preserve authors' copyright notices. KNOWN ISSUES One known problem with the PCMCIA driver is that sometimes when the reader is inserted the PCMCIA support will recognize a memory card instead of the GPR400. Just ejecting the card reader and then reinserting it will fix the problem. The smartcard reader is currently associated with a device having major number 123, minor number 0. You have to create the device manually with: mknod /dev/gpr400 c 123 0 # as root! chmod 0666 /dev/gpr400 # as root! This device number is in the experimental range and currently is not registered with D. Hinds. There is no manpage for this module yet. Documented incompatibility with some Schlumberger cards. I personally know the Cyberflex Access 16k does not work with this reader. Gemplus has acknowledged a hardware problem but has not provided me with suitable information or documentation on how to work around the issues. If you need this to work please help me put pressure on Gemplus to release the necessary information to us. Misc instability problems causing system crashes and such. For example, removing the hardware while the device is open could cause PCMCIA to hang, Linux to crash and/or your teeth to fall out. The most helpful thing you can do in this situation is to provide a patch to the maintainer. Second, you could produce a *complete* bug report including a fool-proof recipe for reproducing the problem. TODO Tend to known issues (duh) Improve power management. Implement T=1 CREDITS The original author of this driver is Wolf Geldmacher . This package was rearranged into the pcmcia-cs project contributed driver format by Joe Phillips . Joe Phillips is the current maintainer of this driver. The package was rearranged again by Henryk Plötz to compile and install with kernel 2.6. See the source files for other credits. TECHNICAL DETAILS Additional notices by Wolf Geldmacher (wolf@comunicon.ch) regarding this derived driver for the GemPlus GPR400 smart card reader: The GPR400 reader has a 2K memory consisting of 2016 bytes attribute memory and external RAM space and 32 bytes I/O buffer. All accesses are performed as byte (i.e. 8 bit) accesses. The optional flash memory (128 k) is not supported. The card information structure is located at address 0x000 in attribute memory. The configuration option register is located at 0xFA0 in the attribute memory. Bit 7 of the configuration register, if set to 1 for at least 5 usec, will initialize the reader. Bit 4..0 specify the I/O port base: I/O Base Configuration Register (bit 4..0) 0x200 - 0x21F 0x10 0x220 - 0x23F 0x11 0x240 - 0x25F 0x12 0x300 - 0x31F 0x18 0x320 - 0x33F 0x19 0x340 - 0x35F 0x1A The general setup register is located at 0xFB8 in the attribute memory and is readonly: bit 4: =0: Attribute memory and I/O buffer locked =1: Attribute memory and I/O buffer accessible other: internal use The smart card register 1 is located at 0xFBA in the attribute memory and is readonly: bit 7: =0: no smart card inserted =1: smart card inserted bit 4: =0: smart card is in the reader =1: smart card was pulled out other: internal use The smart card register 2 at 0xFBC and the clock and control register at 0xFBE in attribute memory are readonly and reserved for internal use. The 32 byte I/O buffer has two control registers at offset 0x00 (handshake and PRG control) and 0x01 (PRG data register). The remaining 30 bytes are used for data exchange with the reader (TLV format). Handshake and Pseudo Randomnumber Generator (PRG) register: bit 0: Master reset. Setting this bit to 1 for a minimum of 5 usec and waiting for 20msec will reset the reader and power it up. bit 1: Interrupt request. After writing a command to the I/O buffer setting this bit to 1 will launch the execution phase. The bit will be reset by the GPR400 after the execution has finished. bit 2: IRQ. This bit is an image of the PCMCIA IREQ pin. The reader sets this bit to 1 after a command has completed, forcing the PCMCIA IREQ line to 0. To acknowledge the interrupt this bit must be reset to 0. bit 3..7: PRG control (not implemented yet)